RSRC LVINLBVW[ [` @<sS[Di8 KrL]]< ُ B~0&ʤbWf=ƚlLVINssformulanode.viLVINSIMSCR Init From Cluster.viD` @0 timingSource@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out4@P @!status @code@0sourceerrorin@ SIMSCR simulation parameters.ctlP@ Initial Time@ Final Time@ Time Step@ Absolute Tolerance@ Relative Tolerance @Discrete Time Step Multiple@0Continuous Solver@0Additional ParametersSimulationParametersPTH0Vaddons Simulation ScriptingCompanion DiagramSIMSCR Init From Cluster.viSIMUSIMMLVINMerge Errors.vi`   6@P @!status @code@0source error outP@@6@P @!status @code@0sourceerror inerror array inB@P @!status @code@0sourceerror in 3 (no error)B@P @!status @code@0sourceerror in 2 (no error)B@P @!status @code@0sourceerror in 1 (no error)PTH0.Utility error.llbMerge Errors.viLVINSIM Set Finished Late Flag.viE x  @dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out@!Finished Late [i-1]@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation dataPTH0Raddons SimulationImplementationSharedSIM Set Finished Late Flag.viSIMUSIMMLVINSIM manager.vi+( @!step complete?@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation dataPTH0Caddons SimulationImplementationSharedSIM manager.viSIMUSIMMLVIN SIM stop.vi) @dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out@!stop simulation?PTH0@addons SimulationImplementationShared SIM stop.viSIMUSIMMLVCC SIMSCR simulation parameters.ctly SIMSCR simulation parameters.ctl@P@ Initial Time@ Final Time@ Time Step@ Absolute Tolerance@ Relative Tolerance @Discrete Time Step Multiple@0Continuous Solver@0Additional Parameters Sim ParamsPTH0[addons Simulation ScriptingCompanion Diagram SIMSCR simulation parameters.ctlSIMUSIMMLVCCSIM limit type.ctl!SIM limit type.ctl(@upperlowerbothnone limit typePTH0Gaddons SimulationImplementationSharedSIM limit type.ctlSIMUSIMMLVCCSIM trigger type.ctl&SIM trigger type.ctl0@risingfallingeithernone trigger typePTH0Iaddons SimulationImplementationSharedSIM trigger type.ctlSIMUSIMMLVIN$SIM Integrator collector (scalar).vi  @dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation dataL@SIM trigger type.ctl"risingfallingeithernone reset type@ upper limit@state array index@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out @ input @ initial condition for reset @ resetD@SIM limit type.ctlupperlowerbothnone limit type@ lower limitPTH0vaddons SimulationContinuousLinearImplementationSIM Integrator.llb$SIM Integrator collector (scalar).viSIMUSIMMLVIN&SIM Integrator distributor (scalar).vi  @dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation dataD@SIM limit type.ctlupperlowerbothnone limit type@ upper limit@state array index@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out @ initial condition for reset @ input @ output@ initial condition@!limited? @ resetL@SIM trigger type.ctl"risingfallingeithernone reset type@ lower limitPTH0xaddons SimulationContinuousLinearImplementationSIM Integrator.llb&SIM Integrator distributor (scalar).viSIMUSIMMLVIN"SIM limit reset states (scalar).vio   @!reset? @ initial condition for resetD@SIM limit type.ctlupperlowerbothnone limit type@ upper limit$@ initial condition for reset out@ lower limitPTH0taddons SimulationContinuousLinearImplementationSIM Integrator.llb"SIM limit reset states (scalar).viSIMUSIMMLVIN0SIM zero cross detect for integrator (scalar).vib   @ inputN@SIM trigger type.ctl"risingfallingeithernone trigger type@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data@!crossed?@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data outPTH0addons SimulationContinuousLinearImplementationSIM Zero Cross Detect.llb0SIM zero cross detect for integrator (scalar).virSIMUSIMMLVCC*AlarmRef__NATIONAL_INSTRUMENTS_lvalarm.ctl8񹯌*AlarmRef__NATIONAL_INSTRUMENTS_lvalarm.ctl>@P @Alarm @Ring @Ring 2 @True Id Timing InfoPTH0XPlatform TimedLoop utilities.llb*AlarmRef__NATIONAL_INSTRUMENTS_lvalarm.ctlLVTLLVTL-LVCC timing.ctl timing.ctlb@P @Period@Initial Offset@ Loop priority@ Timeout (ms)@ Logging Idx@ offset mode@0 Clock Source@0 Loop namep@񹯌*AlarmRef__NATIONAL_INSTRUMENTS_lvalarm.ctl2P @Alarm @Ring @Ring 2 @True Id Ref (out) @@ @NumericReserved4@P @!status @code@0sourceErrorIn Timing outPTH08Platform TimedLoop utilities.llb timing.ctlLVTLLVTL-LVINloadlvalarms.viPTH0APlatform TimedLoopConfigExtNode.llbloadlvalarms.viiLVTLLVTL-LVIN SIM Halt.viJ  @!Halt?@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data outPTH0Aaddons SimulationUtilityImplementation SIM Halt.vi)SIMUSIMMLVINSIM Time Waveform (vector).vi  @@ @ ValueValue@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data@@TP @TPt0@ dt@@ Y2@P @!status @code@0sourceerror@S attributesWaveform Chart@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data outPTH0oaddons Simulation SignalDisplayImplementationSIM Time Waveform.llbSIM Time Waveform (vector).vi)SIMUSIMM=`=`P cP P d-`  P   c,NP"@P@flg@oRt@eofudfP ux dfdP txdP oldP extj Pp@fP0@PP!!!!l@bP0   !!!$@P0!!!B@8PPbPP@TP @TPt0@ dt@@ Y2@P @!status @code@0sourceerror@S attributes000P@TP @TPt0@ dt@@ Y2@P @!status @code@0sourceerror@S attributesb P         @P b P         @P b P         @P  c0PP"@P@flg@oRt@eofudfP@TP @TPt0@ dt@@ Y2@P @!status @code@0sourceerror@S attributesWaveform Chartbp@TTNPTP @ P!0SdfdbP@TTNPTP @ P!0StxdbP@TTNPTP @ P!0SoldbP@TTNPTP @ P!0Sext c,RP"@P@flg@oRt@eofudf P!Halt?x!dfdP!txdP!oldP!ext P    P    P    P    P    P cP"@P@flg@oRt@eofudfP SIMSCR simulation parameters.ctlP@ Initial Time@ Final Time@ Time Step@ Absolute Tolerance@ Relative Tolerance @Discrete Time Step Multiple@0Continuous Solver@0Additional ParametersSimulationParameters2pP     00dfd2PP     00txd2PP     00old2PP     00ext P@P@.P     00"@P@"@P@@P0" P@@D`SIM limit type.ctlupperlowerbothnone limit typeh upper limit h initial condition for reset" P@@h initial condition h resetD`SIM limit type.ctlupperlowerbothnone limit type" P@@L`SIM trigger type.ctl"risingfallingeithernone reset typeh lower limith upper limit h initial condition for reseth initial condition h reset" P@@L`SIM trigger type.ctl"risingfallingeithernone reset typeh lower limit" P@@" P@@r` timing.ctlVP @Period@Initial Offset@ Loop priority@ Timeout (ms)@ Logging Idx@ offset mode@0 Clock Source@0 Loop namep@񹯌*AlarmRef__NATIONAL_INSTRUMENTS_lvalarm.ctl2P @Alarm @Ring @Ring 2 @True Id Ref (out) @@ @NumericReserved4@P @!status @code@0sourceErrorInTiming< P@@@ @Numeric c c$ c0 c@ c  @ u@!crossed? cL@SIM trigger type.ctl"risingfallingeithernone reset typeD@SIM limit type.ctlupperlowerbothnone limit type@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out@state array index c @ reset @ initial condition for reset @ input  @ output@!limited? cL@SIM trigger type.ctl"risingfallingeithernone reset type c @ reset@!crossed? c@state array index @ reset@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out c @ initial condition for reset D@SIM limit type.ctlupperlowerbothnone limit type c @ output @ input @ resetL@SIM trigger type.ctl"risingfallingeithernone reset type@!limited? c@P @Period@Initial Offset@ Loop Priority@ Timeout (ms) @Log Idx @Mode@0source@0 loop name2P @Alarm @Ring @Ring 2 @True Id@4@P @!status @code@0sourceErrorInTiming c@P @Period@Initial Offset@ Loop Priority@ Timeout (ms) @Log Idx @Mode@0source@0 loop name2P @Alarm @Ring @Ring 2 @True Id@4@P @!status @code@0sourceErrorInTiming cP @Expected end [i-1]@Actual end [i-1]@Expected start [i]@Actual start [i]d@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout Wakeup reason@!Finished Late [i-1] @Period @Offset@Priority@ No change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseMode@@Reserved cP @Period @Offset@Priority@ No change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseMode@@Reserved! c @Period! c@0 timingSource@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? 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SubVI Vers @VersL@nitlVersionedState.ctlP @Version @SDataVersioned DataD@nitlCurState.ctlP<@P @Period@Initial Offset@ Loop priority@ Timeout (ms) @mode@0 Source name@0 Source type@0 Loop namep@񹯌*AlarmRef__NATIONAL_INSTRUMENTS_lvalarm.ctl2P @Alarm @Ring @Ring 2 @True Id Ref (out)@Log to trace tool @@ @NumericReservedTiming$@@ @!Boolean Wired Inputs@!Compile?@!Show as Icons?@S G Only Data@@f@nitlTargetSpecificData.ctl*P@0 Target Name@S Target DataTL Target Specific DataTarget Specific Data State Data d1 kHz 1 kHz Clock L12504337DVTP @Version @SVariant@nitlGOnlyData.ctlP@!Has User Configuredv@nitlVisibleControls.ctlHPB@@2@P@disabled @!Visible @SvalueClusterprops Control Props G Only Data                    L@nitlVersionedState.ctlP @Version @SDataVersioned DataD@nitlCurState.ctlP<@P @Period@Initial Offset@ Loop priority@ Timeout (ms) @mode@0 Source name@0 Source type@0 Loop namep@񹯌*AlarmRef__NATIONAL_INSTRUMENTS_lvalarm.ctl2P @Alarm @Ring @Ring 2 @True Id Ref (out)@Log to trace tool @@ @NumericReservedTiming$@@ @!Boolean Wired Inputs@!Compile?@!Show as Icons?@S G Only Data@@f@nitlTargetSpecificData.ctl*P@0 Target Name@S Target DataTL Target Specific DataTarget Specific Data State Datad1 kHz 1 kHz Clock L16715756<|  L16715548KGG CfgPage InfoZ@SIM CfgPageInfo.ctl2P`@SIM TermDataList.ctl4@*@P@0TypeDesc @SDataCluster TermDataTable@SIM PrevIdxTable.ctl@@P@0Label@Idx^@SIM TermDataSource.ctl2 Config PageInternal TerminalOnlyTerminal Data Source TermIdx ItemTerm Source Table @Vers CfgPageInfoValueSimulation dataWaveform ChartSimulation data out CfgPage Vers @Vers Feedthru Info@Feedthru Info.ctlP`@@D@P@0Term(@@@0String Ind Fed TermsClusterFeedthrough List*@@ @!BooleanFeedthrough Map @Vers @DyanmicFeedbackInfo.ctlP6@FeedbackStyle.ctlstaticdynamicStyle>@FeedbackBehavior.ctlDirectIndirectBehavior@2 CallbackVI@2Direct FT. Imp VI@2Indirect FT. Imp VI@! UserEditableDynamic Feedback InfoFeedthru Info OutPTH0PTH0PTH0Generic SimX Info@SIM GenericSimXInfo.ctlP(@P @Width @Height Dimensions @ColorF@SIM Orientation.ctlForwardBackwardBlock Orientation@@SIM TargetDiag.ctlSimDiagCompDiag Target Diag @VersGeneric SimX Info Generic SimX Vers @Vers SubVI Info 4@SIM SubVIWrapperInfo.ctlP@2 Wrapped SubVI@ CurPolyIdx @Vers@SubVIFancy Icon Style@@@H XTermSpec.ctlzP:@H XRect32.ctlP@t@l@b@rbounds @flags@0attrs @width@@3wImgstSpecTermSpecSubVI Wrapper InfoPTH0^addons Simulation SignalDisplayImplementationSIM Time Waveform.llbSIM Time Waveform.vi !@@ @ ValueValue RR@PZ@ RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioF@Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@P @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limits>@@(@upperlowerbothnone limit type limit typesF@@0@risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data  #@@TP @TPt0@ dt@@ Y2@P @!status @code@0sourceerror@S attributesWaveform Chart VV@PZ@ RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioF@Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@P @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limits>@@(@upperlowerbothnone limit type limit typesF@@0@risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out SubVI Vers @Vers 1 - -Generic SimX Info@SIM GenericSimXInfo.ctlP(@P @Width @Height Dimensions @ColorF@SIM Orientation.ctlForwardBackwardBlock Orientation@@SIM TargetDiag.ctlSimDiagCompDiag Target Diag @VersGeneric SimX Info Generic SimX Vers @Vers SubVI Info 4@SIM SubVIWrapperInfo.ctlP@2 Wrapped SubVI@ CurPolyIdx @Vers@SubVIFancy Icon Style@@@H XTermSpec.ctlzP:@H XRect32.ctlP@t@l@b@rbounds @flags@0attrs @width@@3wImgstSpecTermSpecSubVI Wrapper InfoPTH09addons SimulationUtilityImplementation SIM Halt.vi  @!Halt? RR@PZ@ RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioF@Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@P @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limits>@@(@upperlowerbothnone limit type limit typesF@@0@risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data VV@PZ@ RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioF@Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@P @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limits>@@(@upperlowerbothnone limit type limit typesF@@0@risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out SubVI Vers @Vers%.0f %#_15g %#_15g %#_15g%.0f %#_15g%.0f %#_15g %#_15g %#_15g %#_15g %#_15g%.0f %#_15g%.0f%.0f%.0f%.0f%.0f%.0f%.0f%.0f%.0f%.0f%.0f%.0f%.0fQxDxEDDx0V0PPTDTHPDR88~SF6@P @!status @code@0sourceerror IO  @ input @ output@P@ Initial Time@ Final Time@ Time Step@ Absolute Tolerance@ Relative Tolerance @Discrete Time Step Multiple@0Continuous Solver@0Additional Parameters Sim Params@!limited? @ x1_d @ x2_d @ u"@ Loop priority@@TP @TPt0@ dt@@ Y2@P @!status @code@0sourceerror@S attributesWaveform Chart"@ Timeout (ms)@ Logging Idx@ offset moderbPP@TP @TPt0@ dt@@ Y2@P @!status @code@0sourceerror@S attributes   P@TP @TPt0@ dt@@ Y2@P @!status @code@0sourceerror@S attributes&@0 Clock Source*@@ @ ValueValue"@0 Loop nameH<@P @Alarm @Ring @Ring 2 @True Id Ref (out), @@ @NumericReserved@4@P @!status @code@0sourceErrorIn @Initial Offset @Period>.@P @Period@Initial Offset@ Loop priority@ Timeout (ms)@ Logging Idx@ offset mode@0 Clock Source@0 Loop name<@P @Alarm @Ring @Ring 2 @True Id Ref (out) @@ @NumericReserved4@P @!status @code@0sourceErrorIn Timing out .   @@ @ ValueValue@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data@@TP @TPt0@ dt@@ Y2@P @!status @code@0sourceerror@S attributesWaveform Chart@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out @!Halt?*@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out&@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation datafV@PZ@ RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioF@Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@P @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limits>@@(@upperlowerbothnone limit type limit typesF@@0@risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data outbR@PZ@ RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioF@Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@P @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limits>@@(@upperlowerbothnone limit type limit typesF@@0@risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data   @!Halt?@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out@ @0source @code @!statusr@ timing.ctlVP @Period@Initial Offset@ Loop priority@ Timeout (ms)@ Logging Idx@ offset mode@0 Clock Source@0 Loop namep@񹯌*AlarmRef__NATIONAL_INSTRUMENTS_lvalarm.ctl2P @Alarm @Ring @Ring 2 @True Id Ref (out) @@ @NumericReserved4@P @!status @code@0sourceErrorInTiming @Numeric @True Id    @ inputN@SIM trigger type.ctl"risingfallingeithernone trigger type@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data@!crossed?@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out@!crossed?^N@SIM trigger type.ctl"risingfallingeithernone trigger type   @!reset? @ initial condition for resetD@SIM limit type.ctlupperlowerbothnone limit type@ upper limit$@ initial condition for reset out@ lower limit@ lower limit0$@ initial condition for reset out@ upper limitPD@SIM limit type.ctlupperlowerbothnone limit type, @ initial condition for reset @!reset?!   @dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation dataD@SIM limit type.ctlupperlowerbothnone limit type@ upper limit@state array index@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out @ initial condition for reset @ input @ output@ initial condition@!limited? @ resetL@SIM trigger type.ctl"risingfallingeithernone reset type@ lower limitXL@SIM trigger type.ctl"risingfallingeithernone reset type @ reset&@ initial condition&@state array index z j  @dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation dataL@SIM trigger type.ctl"risingfallingeithernone reset type@ upper limit@state array index@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out @ input @ initial condition for reset @ resetD@SIM limit type.ctlupperlowerbothnone limit type@ lower limit @Ring 2 @Ring @Alarm|p@񹯌*AlarmRef__NATIONAL_INSTRUMENTS_lvalarm.ctl2P @Alarm @Ring @Ring 2 @True Id Ref (out)B2P @Alarm @Ring @Ring 2 @True IdfVP @Period@Initial Offset@ Loop priority@ Timeout (ms)@ Logging Idx@ offset mode@0 Clock Source@0 Loop namep@񹯌*AlarmRef__NATIONAL_INSTRUMENTS_lvalarm.ctl2P @Alarm @Ring @Ring 2 @True Id Ref (out) @@ @NumericReserved4@P @!status @code@0sourceErrorIn2"risingfallingeithernone(upperlowerbothnone@ SIMSCR simulation parameters.ctlP@ Initial Time@ Final Time@ Time Step@ Absolute Tolerance@ Relative Tolerance @Discrete Time Step Multiple@0Continuous Solver@0Additional ParametersSimulationParameters.@0Additional Parameters*@0Continuous Solver, @Discrete Time Step Multiple$@ Relative Tolerance$@ Absolute Tolerance@ Time Step ` T @dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out@!stop simulation?&@!stop simulation? d X( @!step complete?@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data @!step complete? x  @dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out@!Finished Late [i-1]@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data$@!Finished Late [i-1]&P @Period @Offset@Priority@ No change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseMode@@ReservedP @Expected end [i-1]@Actual end [i-1]@Expected start [i]@Actual start [i]d@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout Wakeup reason@!Finished Late [i-1] @Period @Offset@Priority@ No change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseMode@@Reserved@P @Period@Initial Offset@ Loop Priority@ Timeout (ms) @Log Idx @Mode@0source@0 loop name2P @Alarm @Ring @Ring 2 @True Id@4@P @!status @code@0sourceErrorInTimingB2@P @!status @code@0sourceError:*@P @Period@Initial Offset@ Loop priority@ Timeout (ms)@ Logging Idx@ offset mode@0 Clock Source@0 Loop name<@P @Alarm @Ring @Ring 2 @True Id Ref (out) @@ @NumericReserved4@P @!status @code@0sourceErrorInTiming|p`   6@P @!status @code@0source error outP@@6@P @!status @code@0sourceerror inerror array inB@P @!status @code@0sourceerror in 3 (no error)B@P @!status @code@0sourceerror in 2 (no error)B@P @!status @code@0sourceerror in 1 (no error)RB@P @!status @code@0sourceerror in 1 (no error)RB@P @!status @code@0sourceerror in 2 (no error)RB@P @!status @code@0sourceerror in 3 (no error)\P@@6@P @!status @code@0sourceerror inerror array inF6@P @!status @code@0source error out` @0 timingSource@dSIM simulation data.ctlP~@SIM integration method.ctlD RK 1 (Euler)Adams LinearizerRK 3RK 4RK 45BDFRK 2RK 23continuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioj@SIM diagram eval stage.ctl6Init Minor Substep Major Substep Discrete stepDiag Eval Stage@ Substep Index@Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float@SIM solver state data.ctlP @@ @ Numericinputs@@ @ Numericoutputs@@ @ Numericreset$@@ @ Numeric lower limits$@@ @ Numeric upper limitsZ@@D@SIM limit type.ctlupperlowerbothnone limit type limit typesd@@N@SIM trigger type.ctl"risingfallingeithernone trigger type reset types*@@ @ Numericinitial conditions"@@ @ Numeric reset I.C. @@ @!Booleanlimited? State data2@P @!status @code@0sourceerror@ Method Order@!Finished Late [i-1]Simulation data out4@P @!status @code@0sourceerrorin@ SIMSCR simulation parameters.ctlP@ Initial Time@ Final Time@ Time Step@ Absolute Tolerance@ Relative Tolerance @Discrete Time Step Multiple@0Continuous Solver@0Additional ParametersSimulationParameters@4@P @!status @code@0sourceerrorin&@0 timingSourceB2@P @!status @code@0sourceerror@ Final Time"@ Initial TimeP@ Initial Time@ Final Time@ Time Step@ Absolute Tolerance@ Relative Tolerance @Discrete Time Step Multiple@0Continuous Solver@0Additional Parameters<<Ld<<<||TLdTpdd<X| 8x<d(@h(|!&P@h0((!11,1H1`1x28 33 38@> h>(L>?p???@(@T@(@ld@|?pLLpTLdL@(@L??hL?p?Lp@(L@L?LhXHX`XxXY Xx1xYL?p?pLLXX 8?p?p38@> h>(L>?p???@(@T@(@ld@|?pLLpTLdL@(@L??hL?p?Lp@(L@L?LhLLZLpLpLL@(@(????ZLpLpLL?p?pLLddpp@(@(??p?pLLZLpLpLL@(@(????Z[\\@\h\\\\gX@hg|h@q@lr@@rh|@||}@lr@@8p<8|[@TLpLpLLdd@(@(???????x@[ddpx1x((|d0 MD$N}[N~[uN HDtRyarybrSD$Nj[Nk[Input ujY\Second order state-space modelHRrshD$^0$_0 Finn Haugen, February 7 2005ZD.;.;Waveform Chart[D$2|3| Simulation TimeHD"RU D$ AmplitudeHDRVcVcM DuQDb{c{Halt?H$Rm n  `DY!Z!SimulationParametersLDY!`Z!`VDMhZMiZ Final TimeHR`lm`n`XD'h4'i4 Initial TimeHlR:lG:n:UDshsi Time StepHRln^DhiAbsolute ToleranceHTRln^DhiRelative ToleranceHRlngDhiDiscrete Time Step MultipleHRln]D ] ^Continuous SolverHR a- c-aD5]B5^BAdditional ParametersHRHaUHcUHD RTaTaHD$RnTznUz HDR55\DZ(fZ*f SimTime WaveformPD@M@Mx1_d[DVXHalt Simulation[D10Simulation LoopWD L- N- Build ArrayPD, 9=,"9<x1=yPDTaTax2_dXD#J0#L0 Formula NodeVD++ IntegratorMDgKtRgLtRuVDANAN IntegratorNDPK]XPL]Xx2ND>KKX>LKXx1`D9[w9\Sx1_d=x2; x2_d=-x1+u;WD L- N- Build ArrayHD$R \DZ(fZ*f SimTime WaveformgD))SIMSCR Init From Cluster.vi[D"~/"/Merge Errors.viVDLK Input NodeWD9z;y Output NodeaDOQ Simulation While LoopiD$1 $1SIM Set Finished Late Flag.vibD65 Accept Step While LoopZD(5(5SIM manager.viWD(5((5' SIM stop.viHD RW^X^HDRtuXD#J0#L0 Formula Node[DVXHalt SimulationPD, 9=,"9<x1=y`D9[w9\Sx1_d=x2; x2_d=-x1+u;PD@M@Mx1_dPDTaTax2_dND>KKX>LKXx1NDPK]XPL]Xx2MDgKtRgLtRuHDR(5T(5TVDKXKX limit typeHD̢R\i'\ i&HDR[h[h NDKXKX WDKXKX upper limitHDPR[h[hgDK~XKXinitial condition for resetHDR[h[hVD(5(5 limit type]DKXKXinitial conditionHD4R[h[hHDR9F'9 F&HDR8E8E nDkxkx"SIM limit reset states (scalar).viQDKXKXresetHDxR[h[hND(5(5 VDKXKX reset typeHD0R\i'\ i&HD|R[h[h NDKXKX WDKXKX lower limitHDR[h[hWD(5(5 upper limitHDR8E8EpD $SIM Integrator collector (scalar).virDUW&SIM Integrator distributor (scalar).vi|Dn{n{~0SIM zero cross detect for integrator (scalar).vigD(~5(5initial condition for resetHDR8E8ERD/P1OTiming]D(5(5initial conditionHDR8E8EnDHUHU"SIM limit reset states (scalar).viQD(5(5resetHDlR8E8EVD(5(5 reset typeHDR9F'9 F&HD,R8E8E ND(5(5 WD(5(5 lower limitHDдR8E8EHDR&+RD=<PeriodpD $SIM Integrator collector (scalar).virDUW&SIM Integrator distributor (scalar).viHDR&%|DKXKX~0SIM zero cross detect for integrator (scalar).viZD[ZInitial OffsetHDR&1YD[Z Loop priorityHDhR * )XD]\ Timeout (ms)HDR*)WD W V Logging IdxHDR!.&!.%WDYX offset modeHDXR2?(2!f'XD"/\"/[ Clock SourceHDRCP(C!'UD3@S3@R Loop nameUDDQKDQJ Ref (out)HDRW d)W"d4QDGT=G!T<AlarmHDRy(y!'HDxRh u>h"=PDXe7X!e6RingHDTR(!'HDRy )y"(RDiv@i!v?Ring 2HDкR )"(SDzEz!DTrue IdHDR%8'7HD$R@IBHSD?hAgNumericTDMLReservedRD@!?statusHDR )"(PD9!8codeHDR"+$*RDB!AsourceSDA@ErrorInND/817 [D#m%lloadlvalarms.viWDkm SIM Halt.viiDs=s?SIM Time Waveform (vector).viNDDQ%DQ$ susw sw   \\ MM Stop&upperlowerbothnone limit type&upperlowerbothnone limit type.risingfallingeithernone trigger type.risingfallingeithernone trigger type AlarmjFPHPssformulanode.viLVCC SIMSCR simulation parameters.ctlPTH0SIMUSIMM(FPHPHR8(|Hm(`XL(0(\U KC7,  D.The step at the system input goes from 0 to U.8hB R8hHBRHXHM` (4 NM|\ w4 JH  w@P Ab XL :H qw0u0/.-0 H mdp 2H 0bncbncbnc0 20|@p 2H bnbbnbbnbp 0|<UUUUUU|UUUUUU<|UUUUUU<0 0h|@  0 2 -sutx4 6 x`sw0 78|B0 74c|hA  0 7azC0 2 (sx4 FRMi\ w< HtHx (0Dd,TD| p^l4 8e0 G G>~DE @RRR}1V FOx/mx4 DX 8 2H qwz$,  `D @0a`x^a`x z 4 D#]1   |4 N -<  0 k! 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